Origin Cache Coherency
- Memory page is divided in data blocks of 32 words or 128 Bytes each (L2 cache line size)
- Each data request transfers one data block (128 Bytes)
- Each data block has associated presence and state information
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- If a node (HUB) requests a data block, the corresponding presence bit is set and the state of that cache line is recorded
- HUB runs the Cache Coherency protocol, updating the state of the data block and notifying nodes for which the presence bit is set.
Each L2 cache line contains 4 data blocks of 8 words
or 32 Bytes each (L1 data cache line size)
Exclusive: one read-write
Busy: state in transition