PPT Slide

R1xK Family of Processors

• Supports the 64-bit MIPS IV ISA

• 4-way superscalar

• Five separate execution units

• 2 floating point results / cycle

• 4-way deep speculative execution of branches

• Out-of-order execution (48 instruction window)

• Register re-naming

• Two-way set associative non-blocking caches
  • Up to 4 outstanding memory read requests
  • Prefetching of data
  • 1MB to 8MB secondary data cache

• Four user-accessible event counters

MIPS R1x000 is an out-of-order, dynamic-scheduling

superscalar processor with non-blocking caches

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