perfex -t: the Model Cost Table
Costs for IP27 processor MIPS R12000 CPU
Cost Typical Minimum Maximum
Event Counter Name ============================================================================================
0 Cycles............................................. 1.00 clks 1.00 clks 1.00 clks
1 Decoded instructions............................... 0.00 clks 0.00 clks 1.00 clks
2 Decoded loads...................................... 1.00 clks 1.00 clks 1.00 clks
3 Decoded stores..................................... 1.00 clks 1.00 clks 1.00 clks
4 Miss handling table occupancy...................... 0.00 clks 0.00 clks 0.00 clks
5 Failed store conditionals.......................... 1.00 clks 1.00 clks 1.00 clks
6 Resolved conditional branches...................... 1.00 clks 1.00 clks 1.00 clks
7 Quadwords written back from scache........... 8.49 clks 5.90 clks 8.77 clks
8 Correctable scache data array ECC errors........... 0.00 clks 0.00 clks 1.00 clks
9 Primary instruction cache misses..............17.01 clks 4.34 clks 17.01 clks
10 Secondary instruction cache misses............99.89 clks 63.03 clks 99.89 clks
11 Instr misprediction from scache way prediction.. .. 0.00 clks 0.00 clks 1.00 clks
12 External interventions............................. 0.00 clks 0.00 clks 0.00 clks
13 External invalidations............................. 0.00 clks 0.00 clks 0.00 clks
14 ALU/FPU progress cycles............................ 1.00 clks 1.00 clks 1.00 clks
15 Graduated instructions............................. 0.00 clks 0.00 clks 1.00 clks
16 Executed prefetch instructions..................... 0.00 clks 0.00 clks 0.00 clks
17 Prefetch primary data cache misses................. 0.00 clks 0.00 clks 1.00 clks
18 Graduated loads.................................... 1.00 clks 1.00 clks 1.00 clks
19 Graduated stores................................... 1.00 clks 1.00 clks 1.00 clks
20 Graduated store conditionals....................... 1.00 clks 1.00 clks 1.00 clks
21 Graduated floating point instructions........ 1.00 clks 0.50 clks 52.00 clks
22 Quadwords written back from primary data cache..... 3.98 clks 3.14 clks 3.98 clks
23 TLB misses........................................77.78 clks 77.78 clks 77.78 clks
24 Mispredicted branches.............................. 7.28 clks 6.00 clks 8.81 clks
25 Primary data cache misses...................... 8.50 clks 2.17 clks 8.50 clks
26 Secondary data cache misses....................99.89 clks 63.03 clks 99.89 clks
27 Data misprediction from scache way prediction table 0.00 clks 0.00 clks 1.00 clks
28 State of intervention hits in scache.........……………. 0.00 clks 0.00 clks 0.00 clks
29 State of invalidation hits in scache............... 0.00 clks 0.00 clks 0.00 clks
30 Store/prefetch exclusive to clean block in scache.. 1.00 clks 1.00 clks 1.00 clks
31 Store/prefetch exclusive to shared block in scache. 1.00 clks 1.00 clks 1.00 clks