perfex -a -y: Multiplexing Events
Based on 300 MHz IP27 MIPS R12000 CPU
Event Counter Name Counter Value Time (sec) Time (sec) Time (sec)
=========================================================================================================
0 Cycles........................................... 5019528970688 16731.763236 16731.763236 16731.763236
16 Executed prefetch instructions................………... 8606259264 0.000000 0.000000 0.000000
4 Miss handling table occupancy.................….. 5443332412048 18144.441373 18144.441373 18144.441373
18 Graduated loads...............................…... 938555860624 3128.519535 3128.519535 3128.519535
2 Decoded loads..................................... 935411271824 3118.037573 3118.037573 3118.037573
25 Primary data cache misses......................... 83185778832 2356.930400 601.710467 2356.930400
21 Graduated floating point instructions............. 519085469744 1730.284899 865.142450 89974.814756
3 Decoded stores.................................... 413277338336 1377.591128 1377.591128 1377.591128
19 Graduated stores.................................. 411214746144 1370.715820 1370.715820 1370.715820
22 Quadwords written back from primary data cache.... 63439898464 841.635986 664.004271 841.635986
6 Resolved conditional branches..................... 231879145424 772.930485 772.930485 772.930485
26 Secondary data cache misses....................... 1951064336 649.639388 409.918617 649.639388
7 Quadwords written back from scache................ 13451750864 380.684549 264.551100 393.239517
23 TLB misses........................................ 1238242032 321.034884 321.034884 321.034884
9 Primary instruction cache misses.................. 1719354640 97.487408 24.873330 97.487408
24 Mispredicted branches............................. 3744555216 90.867873 74.891104 109.965105
10 Secondary instruction cache misses................ 26286992 8.752692 5.522897 8.752692
31 Store/prefetch exclusive to shared block in scache 1435428608 4.784762 4.784762 4.784762
20 Graduated store conditionals...................... 639716576 2.132389 2.132389 2.132389
5 Failed store conditionals......................... 54079168 0.180264 0.180264 0.180264
30 Store/prefetch exclusive to clean block in scache. 20579264 0.068598 0.068598 0.068598
1 Decoded instructions............................. 3312748123920 0.000000 0.000000 11042.493746
8 Correctable scache data array ECC errors......… 0 0.000000 0.000000 0.000000
11 Instruction mispred from scache way prediction table..166448576 0.000000 0.000000 0.554829
12 External interventions............................ 1584014720 0.000000 0.000000 0.000000
13 External invalidations............................ 3304023728 0.000000 0.000000 0.000000
14 ALU/FPU progress cycles........................... 0 0.000000 0.000000 0.000000
15 Graduated instructions........................... 3268746182224 0.000000 0.000000 10895.820607