agave.tamu.edu -- IBM Regatta p690

The 32 processor IBM Regatta p690 is powered by IBM POWER4 processors that operate at 1.3 GHz. These are organized two per chip, which, in turn, are organized into four-chip Multi-Chip Modules (MCMs). Hence, a 32-processor system consists of four interconnected MCMs. The peak floating-point performance per processor is 5.2 GFLOPs/sec. Belying this impressive performance is a very fast memory subsystem that includes a three-level cache structure. All first (2 L1s) and second (L2) level caches are on-chip. The 1.48MB L2 cache is shared by the two processors in a chip. Most importantly, the L2 caches operate at the same speed as the processors themselves. Only the 32MB L3 cache, one per processor chip, is external. Its controller and directory, however, are on-chip. Cache coherency is settled at the L2 level. The aggregate memory bandwidth is approximately 200 GB/s. The size of main memory is 64GB. Disk space is configured and allocated on two distinct environments: (1) approximately 1.150TB is local, directly attached to the regatta; (2) another ~0.5TB is allocated on the TP9500 raid array that is attached to the ALTIX but has Fiber-Channel (FC) connections to the regatta.